1. Field of the invention
The present invention relates to an electrostatic protection device for use in a semiconductor integrated circuit.
2. Description of related art
Generally, an internal circuit of an LSI (large scaled integrated circuit) is protected from a surge applied to an input terminal, by action of an electrostatic protection device connected to the input terminal. In particular, in a MOS (metal oxide semiconductor) LSI, the surge applied to the input terminal is directly applied to a gate oxide film of an internal circuit, so as to cause an electrostatic destroy or break. In order to prevent this electrostatic destroy or break, for example a conventional electrostatic protection circuit includes an electrostatic protection device provided for an input buffer 100, as shown in FIG. 1. This electrostatic protection device includes a P-channel MOS transistor (called a "PMOS" transistor) TP connected between an input terminal IN and a power supply voltage VDD, and an N-channel MOS transistor (called a "NMOS" transistor) TN connected between the input terminal IN and ground GND. A gate of each of the MOS transistors TP and TN is connected to a source of the transistor itself. The input terminal IN is connected to an input of the input buffer 100. The shown electrostatic protection device will be called a "BVds type" hereinafter.
With this arrangement, a charge generated by application of the surge is discharged through the electrostatic protection device, so that the gate oxide of the internal circuit is protected from the breakdown.
For realizing a high speed operation and a high integration density of the LSI, it is indispensable to reduce the thickness of the gate oxide film, with the result that the surge withstanding property of the gate oxide film inevitably lowers. In the above mentioned "BVds type" of electrostatic protection device, the surge is applied not only to the gate oft the internal circuit but also between the drain and the gate of each of the MOS transistors TP and TN in the electrostatic protection device. If the gate oxide film becomes thin, the oxide film in proximity of the drain becomes to be easily destroyed before carriers are escaped through a source-drain path. In order to overcome this problem, it may be considered to enlarge the size of the electrostatic protection device so as to increase a parasitic capacitance. However, this approach is not suitable to the increase of the integration density of the LSI.
On the other hand, with multi-function of the LSI, there is required an input/output buffer suitable to a level conversion circuit and an active line insertion. In this buffer, a voltage of the input terminal becomes larger than VDD in the course of an operation, in some cases. In this case, a forward direction current flows through a drain-substrate path of the transistor TP in the "BVds type" of electrostatic protection device.
In order to overcome the above mentioned problem, it is known to use a field gate transistor (VT2 transistor) as an electrostatic protection device. For example, as shown in FIG. 2, the input protection circuit is constituted by connecting a field gate transistor QB between the power supply voltage VDD and the input terminal IN and another field gate transistor QB between the input terminal IN and the ground GND.
Referring to FIG. 3, there is shown a diagrammatic section view of the field gate transistor and an NMOS transistor included in the internal circuit, for the purpose of illustrating the electrostatic protection device shown hi FIG. 2.
As shown in FIG. 3, field oxide films 3 and 3A are formed on a principal surface of a P.sup.- silicon substrate (or P.sup.- well) 1 in order to define device formation regions. Under these field oxide films 3 and 3A and under a channel forming region of the NMOS transistor, P regions 2, 2D and 2F are formed.
A gate oxide film 4 for the NMOS transistor zone, is formed on the channel forming region, and a gate electrode is formed on the gate oxide film 4, and a stacked structure of the gate oxide film 4 and the gate electrode is surrounded by a side wall spacer 6. N.sup.+ diffused regions 7 are formed at a surface region of the P.sup.- silicon substrate 1 confined by the field oxide films 3 and 3A and at a surface region of the P.sup.- silicon substrate 1 confined by the field oxide film 3, the gate electrode 5 and the side wall spacer 6. An N.sup.+ contact injection region 12 is formed by ion-implanting impurities through a contact hole formed through an interlayer insulator film 10, and a tungsten plug 13 is filled in the contact hole. In the field gate transistor, a source electrode 31 and a drain electrode 32 are connected through the tungsten plug 13 to the N.sup.+ diffused regions 7 which constitute a source region and a drain region. A gate electrode 33 is formed on the interlayer insulator film 10 directly above the field oxide film 3A. Electrodes 34 of the NMOS transistor are connected through the tungsten plug 13 to corresponding ones such as the gate electrode 5 and the N.sup.+ diffused region 7.
In the above mentioned structure, the field gate transistor is parasitic transistors having a source region and a drain region which are constituted by the N.sup.+ diffused regions 7 adjacent to each other but isolated by the field oxide film 3A. The gate electrode 33 is connected to the drain electrode 32 and the input terminal IN, and also connected through a protection resistor R to the internal circuit 100.
For example, when a positive surge voltage is applied to the input terminal IN of the circuit shown in FIG. 2, the field gate transistor QB is mined on, and therefore, an on-current of the field gate transistor QB flows through a drain (D) - source (S) path, or a junction breakdown current flows through a drain (D) - substrate (d) path, so that a gate oxide film of a transistor in the internal circuit is protected from the surge.
Thus, the field gate transistor QB itself has a sufficient strength withstanding the surge. However, since This surge withstanding voltage of the field gate transistor QB is high as mentioned above, the function for protecting the internal circuit from the surge is low.
For example, in a CMOS LSI having a gate length on the order of 0.3 .mu.m, a surface impurity concentration of the P type region is set to be on the order of 2.times.10.sup.17 cm .sup.-3 to 3.times.10.sup.17 cm.sup.-3. Therefore, the junction breakdown voltage between the N.sup.+ diffused region 7 and the P type region 2D is on the order of 15 V even if the P type region were formed formed on the whole surface. In addition, since the thickness of the field oxide 3A and the interlayer insulator film 10 (constituting the gate insulator film of the field gate transistor) is set to be 1 .mu.m or more in total. Therefore, the turning-on voltage of the field gate transistor itself is far higher than the above mentioned drain junction breakdown voltage.
On the other hand, the film thickness of the gate oxide film 4 in the MOS transistor in the internal circuit is set to be 7 nm to 8 nm in the case of the gate length 0.3 .mu.m process. Therefore, if an intrinsic breakdown electric field of 10 MV/cm or more, namely, a voltage of 8 V or more is directly applied to the gate oxide, the gate oxide film is broken down or destroyed.
Considering only the DC current, in the CMOS LSI of the gate length 0.3 .mu.m process incorporating therein the conventional electrostatic protection device, there is possibility that a bias on the order of 15 V far larger than the breakdown voltage of the gate oxide film is applied to the internal circuit. Considering a sufficient protection from the surge input which is practically a problem, it is necessary to cause the electrostatic protection device to have a very large parasitic capacitance for sufficiently lowering an initial voltage of the surge, with the result that the size of the electrostatic protection device becomes large. This is opposite to the high integration density of the LSI.
For example, in order to ensure the surge withstanding property without increasing the size of the electrostatic protection device, it is necessary to lower the breakdown voltage of the electrostatic protection device itself. For this purposes, two approaches may be considered. A first approach is to lower the breakdown voltage of the electrostatic protection device by causing a punch-through between the drain and the source of the field gate transistor. The second approach is to lower the breakdown voltage of the drain-substrate junction. A method for causing a punch-through between the drain and the source, includes (A) a method of lowering the concentration of the P-type region 2D isolating between the N.sup.+ region and the N.sup.+ region, and (B) a method of reducing the distance L2 of the separation between the N.sup.+ region and the N.sup.+ region.
Since the P-type regions 2D and 2F are formed in the same step, if the concentration of the P-type region 2D is lowered in accordance with the method (A), the concentration of the P-type region 2F in the NMOS transistor forming region is similarly lowered, with the result that a punch-through becomes to easily occur between the drain and the source of the NMOS transistor. Accordingly, a transistor having the gate length of a sub micron order becomes very difficult to design. Furthermore, another problem occurs in which there drops a turn-on voltage of a parasitic field gate transistor constituted of the gate of the gate oxide 33, the oxide film of the field oxide film 3 and source/drain regions of adjacent N.sup.+ diffused regions separated by the field oxide film 3. Therefore, in order to avoid this problem, it is necessary to optimize the concentration of the two P-type regions. In the example shown in FIG. 3, however, this means that the P-type region 2D and the P-type region 2F must be formed m different steps, with the result that the number of photo masks and the steps of the manufacturing process are increased.
In the method (B) of reducing the distance L2 of the separation between the N.sup.+ region and the N.sup.+ region, since variation or fluctuation of the breakdown voltage is large, it is not possible to obtain a stable surge withstanding voltage. For example, assuming that the concentration of the P-type region 2D is 3.times.10.sup.17 cm .sup.-3, in order to obtain the punch-through withstanding voltage on the order of 8 V, the separation length L2 is required to be reduced to the order of 0.4 .mu.m. Since the N.sup.+ --N.sup.+ separation length L2 is determined by the length of the field oxide film 3, a stable size cannot be obtained due to manufacturing variations or fluctuations in various factors such as a precision degree of a photo resist for defining the field oxide film region, a bird's beak length and the field oxide film thickness. In other words, the punch-through withstanding voltage inevitably becomes large in variation.
Finally, the method of lowering the breakdown voltage of the drain-substrate junction includes increasing the concentration of the P-type region 2D. However, in order to lower the breakdown voltage of the drain-substrate junction with giving no influence to the characteristics of the NMOS transistor, it is necessary to increase the concentration of only the P-type region 2D. Therefore, the P-type region 2D and the P-type region 2F must be formed in different steps, with the result that the number of photo masks and the steps of the manufacturing process are increased.